The present invention relates to a phase adjustment circuit which adjusts delay dispersion that occurs during clock distribution in a logic IC and logic card.
In a conventional logic IC and logic card, a phase adjustment circuit which compares the phases of a reference clock signal supplied from an external device and the phase of a feedback clock signal which shows that delay occurs during internal clock distribution. The phase adjustment circuit controls delay time in the internal clock distribution based on the result of the comparison so that the phase of the feedback clock signal becomes identical to the phase of the reference clock signal.
As the performance of a logic device is enhanced, the clock frequency in a central processing unit and its peripheral devices is increased. However, the clock frequency in an input/output device, a diagnostic device and others is not as high compared to the clock frequency in a central processing unit or its peripheral devices. Therefore, the distribution of a plurality of different of clock signals to one logic IC or one logic card is often required. A plurality of phase adjustment circuits described above is provided for every type of a clock in a single chip.
Referring to FIG. 4, a conventional phase adjustment circuit includes three phase-locked loop (PLL) circuits 100a to 100c, logic devices 20a-1 to 20a-n connected to PLL circuit 100a, logic devices 20b-1 to 20b-n connected to PLL circuit 100b and logic devices 20c-1 to 20c-n connected to PLL circuit 100c.
PLL circuit 100a includes a variable delay circuit 10a, a phase comparing circuit 30a and a counter 40a. Variable delay circuit 10a, to which a clock signal CK0 having a predetermined cycle is input, delays clock signal CK0 by a set delay time and outputs it. Phase comparing circuit 30a compares the phase of a feedback clock signal CFB0, which is output from the variable delay circuit 10a and delayed during internal clock distribution, and the phase of a reference clock signal CREF0 input from an external device. Counter 40a increases or decreases its counted value based on the result of the comparison by phase comparing circuit 30a. The delay time used in the variable delay circuit 10a is set based on a value counted by counter 40a.
PLL circuit 100b includes a variable delay circuit 10b, a phase comparing circuit 30b and a counter 40b. Variable delay circuit 10b, to which a clock signal CK1 having a predetermined cycle is input, delays clock signal CK1 by a set delay time and outputs it. Phase comparing circuit 30b compares the phase of a feedback clock signal CFB1, which is output from the variable delay circuit 10b and delayed during internal clock distribution, and the phase of a reference clock signal CREF1 input from an external device. Counter 40b increases or decreases its counted value based on the result of the comparison by phase comparing circuit 30b. The delay time used in the variable delay circuit 10b is set based on a value counted by counter 40b.
PLL circuit 100c includes a variable delay circuit 10c, a phase comparing circuit 30c and a counter 40c. Variable delay circuit 10c, to which a clock signal CK2 having a predetermined cycle is input, delays clock signal CK2 by a set delay time and outputs it. Phase comparing circuit 30c compares the phase of a feedback clock signal CFB2, which is output from the variable delay circuit 10c and delayed during internal clock distribution, and the phase of a reference clock signal CREF2 input from an external device. Counter 40c increases or decreases its counted value based on the result of comparison by phase comparing circuit 30c. The delay time used in the variable delay circuit 10c is set based on a value counted by counter 40c.
Clock signals CK0 to CK2 are delayed in variable delay circuits 10a to 10c, respectively, so that each phase of clock signals CFB0 to CFB2, which are delayed during clock distribution in PLL circuits 100a to 100c, become identical to each phase of reference clock signals CREF0 to CREF2, respectively. Thus, the time at which the clock signals CK0, CK1 and CK2 are supplied to logic devices 20a-1 to 20a-n, 20b-1 to 20b-n and 20c-1 to 20c-n, respectively, is adjusted.
However, it is necessary to provide the same number of PLL circuits and reference clock signal input terminals as the number of the phase adjustment circuits when a plurality of phase adjustment circuits are provided in the same chip. This creates a problem because the scale of the hardware becomes large.
While the same reference clock signal is input to the PLL circuits, it is input to the plurality of input terminals and its phase is compared to the phase of a feedback clock signal in the plurality of phase comparing circuits. This creates a problem because a slight error may be produced between the reference clock signals. The error depends on the precision of a circuit which supplies a reference clock signal and dispersion among the characteristics of the phase comparing circuits.